Web74HC_HCT138 Datasheet - Free download as PDF File (.pdf), Text File (.txt) or read online for free. datashheet de esta compuerta logica. datashheet de esta compuerta logica. 74HC - HCT138 Datasheet. Uploaded by Fabian Monge. 0 ratings 0% found this document useful (0 votes) 23 views. 17 pages. Web1. General description The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
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WebThe 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0to Y7). The “138” … WebThe AiP74HC/HCT138 decodes three binary weighted address inputs(A0, A1 and A2) to eight mutually exclusive outputs (Y — 0 to Y — 7). The device features three enable inputs (E — 1, E — 2 and E3). Every output will be HIGH unless E — 1 and E — 2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel playing pere card
74HC HCT138 PDF Electrical Circuits Electrical Engineering
WebThe ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed silicon-gate CMOS decoders well suited to memory address decoding or data-routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL logic. Both circuits have three binary select ... Web手机版 芯视频 app 微信公众号 维库官方抖音 微信头条号 Web74VHCT138: 64Kb / 8P: 3 TO 8 LINE DECODER INVERTING Texas Instruments: CD5474HCT138: 765Kb / 19P [Old version datasheet] High-Speed CMOS Logic 3- to 8 … playing own music on alexa